1. Field of the Invention
The invention relates to programmable integrated circuit devices, more particularly to a Configurable Logic Element (CLE) in a field programmable logic device.
2. Description of the Background Art
Field Programmable Gate Arrays (FPGAs) typically include an array of tiles. Each tile includes a Configurable Logic Element (CLE) connectable to CLEs in other tiles through programmable interconnect lines. The interconnect lines typically provide for connecting each CLE to each other CLE.
CLEs typically include combinatorial function generators, which are often implemented as 4-input lookup tables.
Some CLEs can also implement any 5-input function by selecting between the outputs of two 4-input function generators with another CLE input. One such CLE, implemented in the Xilinx XC4000-Series FPGAs, is described in pages 4-11 through 4-23 of the Xilinx 1996 Data Book entitled "The Programmable Logic Data Book", available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124, which are incorporated herein by reference. (Xilinx, Inc., owner of the copyright, has no objection to copying these and other pages referenced herein but otherwise reserves all copyright rights whatsoever.) A portion of an XC4000-Series CLE implementing a 5-input function generator is shown in FIG. 1. The outputs F' and G' of the two function generators F and G can be optionally combined with a third signal H1 in a third function generator 3H to form output 3H'. The 3H function generator can implement any function of the three inputs (256 functions), including a 2-to-1 multiplexer that can be used when a 5-input function is desired. When function generators F and G share the same four inputs (F1/G1, F2/G2, F3/G3, F4/G4) and function generator 3H is programmed to function as a 2-to-1 multiplexer, output 3H' can represent any function of up to five inputs (F1/G1, F2/G2, F3/G3, F4/G4, H1). When the inputs to function generators F and G are independent, output 3H' can represent some functions of up to nine inputs (F1, F2, F3, F4, G1, G2, G3, G4, H1).
Function generator 3H can be replaced by a 2-to-1 multiplexer, with signal H1 selecting between outputs F' and G', as disclosed in U.S. Pat. No. 5,349,250 entitled "Logic Structure and Circuit for Fast Carry" by Bernard J. New, which is incorporated herein by reference. Replacing the function generator of FIG. 1 with a 2-to-1 multiplexer reduces the number of supported functions with up to nine inputs, but still provides any function of up to five inputs and reduces the silicon area required to implement a five-input-function generator. An FPGA using two 4-input function generators and a 2-to-1 multiplexer to implement a five input function generator is the XC5200.TM. family of products from Xilinx, Inc. The XC5200 CLE is described in pages 4-188 through 4-190 of the Xilinx 1996 Data Book entitled "The Programmable Logic Data Book", available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124, which are incorporated herein by reference.
A CLE capable of generating 6-input functions is described as implemented in the ORCA.TM. OR2C FPGAs from Lucent Technologies Inc. ("ORCA" is a trademark of Lucent Technologies Inc.) This CLE is described in pages 2-9 through 2-20 of the Lucent Technologies October 1996 Data Book entitled "Field-Programmable Gate Arrays", available from Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, Pa. 18103, which are incorporated herein by reference. A portion of an ORCA OR2C CLE implementing a 6-input function generator is shown here in FIG. 2. The CLE of FIG. 2 comprises four 4-input function generators QLUT0, QLUT1, QLUT2, QLUT3. Function generator QLUT0 has four inputs B0, B1, B2, B3 and function generator QLUT1 has four inputs B1, B2, B3, B4. Outputs QL0 and QL1 of function generators QLUT0 and QLUT1, respectively, can be selected between in 2-to-1 multiplexer MUX0 with CLE input signal B4 acting as a select line to form output M0. Multiplexer MUX0 therefore can provide functions of five input signals B0, B1, B2, B3, B4. Similarly, function generator QLUT2 has four inputs A0, A1, A2, A3 and function generator QLUT3 has four inputs A1, A2, A3, A4. Outputs QL2 and QL3 of function generators QLUT2 and QLUT3, respectively, can be optionally combined in 2-to-1 multiplexer MUX3 with CLE input signal A4 acting as a select line to form output M3. Multiplexer MUX3 therefore can provide functions of five input signals A0, A1, A2, A3, A4. Multiplexer outputs M0 and M3 can optionally be combined in 2-to-1 multiplexer MUX6 with CLE input signal C0 acting as a select line to form output M1. When input signals A0, A1, A2, A3, A4 are shared with input signals B0, B1, B2, B3, B4, respectively, multiplexer output M1 can represent functions of up to six inputs (A0/B0, A1/B1, A2/B2, A3/B3, A4/B4, C0).
One advantage of including four function generators in a single CLE is the ability to implement circuits requiring three or four function generators, such as 6-input functions, in a single CLE, thereby improving the performance of the circuit. (Connections between CLE outputs and inputs are typically slower than internal connections within a single CLE.) However, one disadvantage is that the resulting software model for the CLE is more complicated than the software model for a smaller, simpler CLE. FPGA mapping, placing, routing, and delay estimation software tools require a CLE software model in order to implement a user's design. The more complicated the CLE software model, the more complicated it becomes to write the mapping, placing, routing, and delay estimation software, and the longer the software takes to run. Therefore, it is desirable to increase the number of function generators in a CLE without increasing the complexity of the software model.
Additionally, the amount of logic that can be placed in an FPGA is often limited by the amount of interconnect available, particularly in high-density designs (i.e., designs using a high percentage of the available logic blocks). Adding enough interconnect lines to support high-density designs allows a larger percentage of the available logic blocks to be used, but is costly in terms of silicon area because of the silicon required to programmably interconnect the lines. The silicon area for the extra interconnect lines is wasted for designs that do not require the extra interconnect lines. It is therefore desirable to minimize the number of required interconnect lines, rather than adding additional lines for high-density designs.